Preparation and processing of big data during of industrial testing of VLSI

Author(s)

Abstract
The integration level of modern VLSI allows developers to place an entire digital device on a chip (System-oт-Chip technology), which dramatically increases the amount of data on testing such VLSI. The most alarming situation is observed when testing VLSI memory, which is both an independent VLSI and one of the main blocks of а digital system. The process of their production includes up to 1000 technological and control operations, for which it is necessary to memorize hundreds of parameters. As a result, testing the memory required for practice by modern VLSI methods may take several years. The article proposes a hardware and software complex for industrial testing of VLSI, in which the developer is excluded from the two-way chain «algorithm of testing  topology», which made it possible to effectively implement the mechanism for localizing of the topology errors by directly linking them with test vectors. The client-server system of the «Sigma Viewer» complex and the «Lorenz» data analysis environment are described, which, using the new original «RSTL» data format, provide storage and processing of an almost unlimited amount of interoperational exchange metadata. The complex operating on the basis of the «STeeL» language, capable of processing hundreds of thousands of test vectors in real time.

Keywords
industrial testing of VLSI, big data on testing of VLSI, software, hidden defects of integral structures

Cite this paper
Konstantin Smirnov, Alexander Nazarov, Alexander Engalychev, Preparation and processing of big data during of industrial testing of VLSI , SCIREA Journal of Materials. Volume 5, Issue 2, April 2020 | PP. 17-28.

References